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fully accurate 16-bit v out nano dac spi interface 2.7 v to 5.5 v in an msop ad5063 rev. c information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2005C2009 analog devices, inc. all rights reserved. features single 16-bit dac, 1 lsb inl power-on reset to midscale guaranteed monotonic by design 3 power-down functions low power serial interface with schmitt-triggered inputs 10-lead msop, low power fast settling time of 1 s maximum (ad5063-1 model) 2.7 v to 5.5 v power supply low glitch on power-up unbuffered voltage capable of driving 60 k load sync interrupt facility applications process control data acquisition systems portable battery-powered instruments digital gain and offset adjustment programmable voltage and current sources programmable attenuators functional block diagram ad5063 v dd v out v ref power-on reset dac register dac input control logic power-down control logic resistor network ref(+) sclk din 04766-001 sync dacgnd buf a gnd r fb inv figure 1. table 1. related devices part no. description ad5061 2.7 v to 5.5 v, 16-bit nano dac d/a, 4 lsbs inl, sot-23. ad5062 2.7 v to 5.5 v, 16-bit nano dac d/a, 1 lsb inl, sot-23. ad5040 / ad5060 2.7 v to 5.5 v, 14-/16-bit nano dac d/a, 1 lsb inl, sot-23. general description the ad5063, a member of adis nano dac? family, is a low power, single 16-bit, unbuffered voltage-output dac that operates from a single 2.7 v to 5 v supply. the part offers a relative accuracy specification of 1 lsb, and operation is guaranteed monotonic with a 1 lsb dnl specification. the ad5063 comes with on-board resistors in a 10-lead msop, allowing bipolar signals to be generated with an output amplifier. the part uses a versatile 3-wire serial interface that operates at clock rates up to 30 mhz and that is compatible with standard spi?, qspi?, microwire?, and dsp interface standards. the reference for the ad5063 is supplied from an external v ref pin. a reference buffer is also provided on-chip. the part incor- porates a power-on reset circuit that ensures the dac output powers up to midscale and remains there until a valid write to the device takes place. the part contains a power-down feature that reduces the current consumption of the device to typically 300 na at 5 v and provides software-selectable output loads while in power-down mode. the part is put into power-down mode via the serial interface. total unadjusted error for the part is <1 mv. this part exhibits very low glitch on power-up. product highlights available in 10-lead msop. 16-bit accurate, 1 lsb inl. low glitch on power-up. high speed serial interface with clock speeds up to 30 mhz. three power-down modes available to the user.
ad5063 rev. c | page 2 of 2 0 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 product highlights ........................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 timing characteristics ................................................................ 5 absolute maximum ratings ............................................................ 6 esd caution .................................................................................. 6 pin configuration and function descriptions ............................. 7 typical performance characteristics ............................................. 8 terminology .................................................................................... 12 theory of operation ...................................................................... 13 dac architecture ....................................................................... 13 reference buffer ......................................................................... 13 serial interface ............................................................................ 13 input shift register .................................................................... 13 sync interrupt .......................................................................... 13 power-on to midscale ............................................................... 14 software reset ............................................................................. 14 power-down modes .................................................................. 14 microprocessor interfacing ....................................................... 14 applications ..................................................................................... 16 choosing a reference for the ad5063 .................................... 16 bipolar operation using the ad5063 ..................................... 16 using the ad5063 with a galvanically isolated interface chip ............................ 17 power supply bypassing and grounding ................................ 17 outline dimensions ....................................................................... 18 ordering guide .......................................................................... 18 revision history 8/09rev. b to rev. c changes to features section............................................................ 1 changes to output voltage settling time parameter, table 2 ... 3 updated outline dimensions ....................................................... 18 changes to ordering guide .......................................................... 18 3/06rev. a to rev. b updated format .................................................................. universal change to features ........................................................................... 1 change to figure 1 ........................................................................... 1 changes to specifications ................................................................ 3 change to absolute maximum ratings ......................................... 6 change to reference buffer section ............................................ 13 change to serial interface section ............................................... 13 change to table 6 ........................................................................... 14 change to bipolar operation using the ad5063 section ........ 16 7/05rev. 0 to rev. a changes to galvanically isolated chip section .......................... 17 changes to figure 38 ...................................................................... 17 4/05revision 0: initial version
ad5063 rev. c | page 3 of 20 specifications v dd = 2.7 v to 5.5 v, v ref = 4.096 v @ v dd = 5.0 v, r l = unloaded, c l = unloaded to gnd; t min to t max , unless otherwise noted. table 2. b version 1 parameter min typ max unit test conditions/comments static performance resolution 16 bits relative accuracy (inl) 0.5 1 lsb ?40c to + 85c, b grade over all codes total unadjusted error (tue) 500 800 v differential nonlinearity (dnl) 0.5 1 lsb guaranteed monotonic gain error 0.01 0.02 % fsr t a = ?40c to +85c gain error temperature coefficient 1 ppm fsr/c zero-code error 0.05 0.1 mv all 0s loaded to dac register, t a = ?40c to +85c zero-code error temperature coefficient 0.05 v/c offset error 0.05 0.1 mv t a = ?40c to +85c offset error temperature coefficient 0.5 v/c full-scale error 500 800 v all 1s loaded to dac register, t a = ?40c to +85c bipolar resistor matching 1 / r fb /r inv , r fb = r inv = 30 k typically bipolar zero offset error 8 16 lsb bipolar zero temperature coefficient 0.5 ppm fsr/c bipolar gain error 16 32 lsb output characteristics 2 output voltage range 0 v ref v unipolar operation ?v ref v ref v bipolar operation output voltage settling time 3 ? scale to ? scale code transition to 1 lsb ad5063brmz 4 s ad5063brmz-1 1 s v dd = 4.5 v to 5.5 v 4 s v dd = 2.7 v to 5.5 v output noise spectral density 64 nv/hz dac code = midscale, 1 khz output voltage noise 6 v p-p dac code = midscale, 0.1 hz to 10 hz bandwidth digital-to-analog glitch impulse 2 nv-s 1 lsb change around major carry digital feedthrough 0.002 nv-s dc output impedance (normal) 8 k output impedance tolerance 10% dc output impedance (power-down) (output connected to 1 k network) 1 k output impedance tolerance 400 (output connected to 10 k network) 100 k output impedance tolerance 20 k reference input/ouput v ref input range 2 v dd ? 50 mv input current (power-down) 1 a zero-scale loaded input current (normal) 1 a dc input impedance 1 m bipolar/unipolar operation logic inputs input current 4 1 2 a input low voltage, v il 0.8 v v dd = 4.5 v to 5.5 v 0.8 v dd = 2.7 v to 3.6 v input high voltage, v ih 2.0 v v dd = 2.7 v to 5.5 v 1.8 v dd = 2.7 v to 3.6 v pin capacitance 4 pf
ad5063 rev. c | page 4 of 20 b version 1 parameter min typ max unit test conditions/comments power requirements v dd 2.7 5.5 v all digital inputs at 0 v or v dd i dd (normal mode) dac active and excluding load current v dd = 4.5 v to 5.5 v 0.65 0.7 ma v in = v dd and v il = gnd, v dd = 5 v, v ref = 4.096 v, code = midscale v dd = 2.7 v to 3.6 v 0.5 ma v ih = v dd and v il = gnd, v dd = 3 v i dd (all power-down modes) v dd = 4.5 v to 5.5 v 1 a v ih = v dd and v il = gnd v dd = 2.7 v to 3.6 v 1 a v ih = v dd and v il = gnd power supply rejection ratio (psrr) 0.5 lsb ?v dd 10%, v dd = 5 v, unloaded 1 temperature ranges for the b version: ?40c to +85c, typical at +25c, functional to +125c. 2 guaranteed by design and characterization, not production tested. 3 see the ordering guide. 4 total current flowing into all pins.
ad5063 rev. c | page 5 of 20 timing characteristics v dd = 2.7 v to 5.5 v; all specifications t min to t max , unless otherwise noted. table 3. parameter limit 1 unit test conditions/comments t 1 2 33 ns min sclk cycle time t 2 5 ns min sclk high time t 3 3 ns min sclk low time t 4 10 ns min sync to sclk falling edge setup time t 5 3 ns min data setup time t 6 2 ns min data hold time t 7 0 ns min sclk falling edge to sync rising edge t 8 12 ns min minimum sync high time t 9 9 ns min sync rising edge to next sclk fall ignore 1 all input signals are specified with t r = t f = 1 ns/v (10% to 90% of v dd ) and timed from a voltage level of (v il + v ih )/2. 2 maximum sclk frequency is 30 mhz. t 4 t 3 t 2 t 5 t 7 t 6 d0 d1 d2 d22 d23 sync sclk 04766-002 t 9 t 1 t 8 d23 d22 din figure 2. timing diagram
ad5063 rev. c | page 6 of 20 absolute maximum ratings table 4. parameter rating v dd to gnd ?0.3 v to +7.0 v digital input voltage to gnd ?0.3 v to v dd + 0.3 v v out to gnd ?0.3 v to v dd + 0.3 v v ref to gnd ?0.3 v to v dd + 0.3 v inv to gnd ?0.3 v to v dd + 0.3 v r fb to gnd +7 v to ?7 v operating temperature range industrial (b version) ?40c to + 85c 1 storage temperature range ?65c to +150c maximum junction temperature 150c msop package power dissipation (t j max ? t a )/ ja ja thermal impedance 206c/w jc thermal impedance 44c/w reflow soldering (pb-free) peak temperature 260(0/?5)c time at peak temperature 10 sec to 40 sec esd 1.5 kv 1 temperature range for this device is ? 40c to +85c; however, the device is still operational at 125c. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. this device is a high performance integrated circuit with an esd rating of <2 kv, and it is esd sensitive. proper precautions should be taken for handling and assembly. esd caution esd (electrostatic discharge) sensitive device. electros tatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge wi thout detection. although this product features proprietary esd protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
ad5063 rev. c | page 7 of 20 pin configuration and fu nction descriptions ad5063 top view (not to scale) v out sync 11 0 agnd sclk 29 din dacgnd 38 04766-003 v ref 47 v dd inv r fb 56 figure 3. pin configuration table 5. pin function descriptions pin no. mnemonic description 1 din serial data input. this device has a 24-bit shift register. da ta is clocked into the register on the falling edge of the serial clock input. 2 v dd power supply input. these parts can be operated from 2.7 v to 5.5 v, and v dd should be decoupled to gnd. 3 v ref reference voltage input. 4 v out analog output voltage from dac. 5 inv connected to the internal scaling resistors of the dac. connect the inv pin to the external op amps inverting input in bipolar mode. 6 r fb feedback resistor. in bipolar mode, connect this pin to the external op amp circuit. 7 agnd ground reference point for analog circuitry. 8 dacgnd ground input to the dac. 9 sync level-triggered control input (active low). this is th e frame synchronization signal for the input data. when sync goes low, it enables the input shift register, and data is then transferred in on the falling edges of the following clocks. the dac is updated following the 24 th clock cycle unless sync is taken high before this edge, in which case the rising edge of sync acts as an interrupt, and the write sequence is ignored by the dac. 10 sclk serial clock input. data is clocked into the input shift register on the falling edge of the serial clock input. data can be transferred at rates of up to 30 mhz.
ad5063 rev. c | page 8 of 20 typical performance characteristics 04766-047 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 0 10000 20000 30000 40000 50000 60000 70000 dac code inl error (lsb) 1.2 1.4 t a = 25c v dd = 5v v ref = 4.096v 04766-046 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 0 10000 20000 30000 40000 50000 60000 70000 dac code dnl error (lsb) t a = 25c v dd = 5v v ref = 4.096v figure 4. inl error vs. dac code figure 7. dnl error vs. dac code 04766-048 0 10000 20000 30000 40000 50000 60000 70000 dac code tue error (mv) ?0.10 ?0.08 ?0.06 ?0.04 ?0.02 0 0.02 0.04 0.06 0.08 0.10 t a = 25c v dd = 5v v ref = 4.096v ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 ?40 ?20 0 20 40 60 80 100 120 140 temperature (c) dnl error (lsb) v dd = 5.5v v ref = 4.096v v dd = 2.7v v ref = 2.0v max dnl @ v dd = 5.5v max dnl @ v dd = 2.7v min dnl @ v dd = 2.7v min dnl @ v dd = 5.5v 04766-013 figure 5. tue error vs. dac code figure 8. dnl error vs. temperature v dd = 5.5v v ref = 4.096v v dd = 2.7v v ref = 2.0v ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0.2 0.4 0.6 0.8 1.0 ?40 ?20 0 20 40 60 80 100 120 140 temperature (c) tue error (lsb) 04766-009 max tue @ 2.7v max tue @ 5.5v min tue @ 5.5v min tue @ 2.7v 0 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 1.2 ?40 ?20 0 20 40 60 80 100 120 140 temperature (c) inl error (lsb) 04766-012 v dd = 5.5v v ref = 4.096v v dd = 2.7v v ref = 2.0v max inl @ v dd = 2.7v max inl @ v dd = 5.5v min inl @ v dd = 2.7v min inl @ v dd = 5.5v figure 6. inl error vs. temperature figure 9. tue error vs. temperature
ad5063 rev. c | page 9 of 20 ?3 ?2 ?1 0 1 2 3 1 reference voltage (v) inl error (lsb) t a = 25c max inl @ v dd = 5.5v min inl @ v dd = 5.5v 6 2345 04766-004 figure 10. inl error vs. reference input voltage ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 1 reference voltage (v) dnl error (lsb) t a = 25c 6 2345 min dnl v dd = 5.5v max dnl v dd = 5.5v 04766-044 figure 11. dnl error vs. reference input voltage ?0.10 ?0.08 ?0.06 ?0.04 ?0.02 0 0.02 0.04 0.06 0.08 0.10 1 reference voltage (v) tue error (mv) t a = 25c 6 2345 min tue @ v dd = 5.5v max tue @ v dd = 5.5v 04766-005 figure 12. tue error vs. reference input voltage ?0.25 ?0.20 ?0.15 ?0.10 ?0.05 0 0.05 0.10 0.15 0.20 0.25 offset (mv) ?40 ?20 0 20 40 60 80 100 120 140 temperature (c) v dd = 5.5v v ref = 4.096v v dd = 2.7v v ref = 2.0v max offset @ v dd = 5.5v max offset @ v dd = 2.7v 04766-007 figure 13. offset vs. temperature 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 ?40 ?20 0 20 40 60 80 100 120 140 temperature (c) supply current (ma) 04766-041 v dd = 3v v ref = 2.7v v dd = 5.5v v ref = 4.096v figure 14. supply current vs. temperature 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0 10000 20000 30000 40000 50000 60000 70000 digital input code supply current (ma) 04766-042 t a = 25c v dd = 5.5v v ref = 4.096v v dd = 3v v ref = 2.5v figure 15. supply current vs. digital input code
ad5063 rev. c | page 10 of 20 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 2.7 3.2 3.7 4.2 4.7 5.2 5.7 supply voltage (v) supply current (ma) 04766-043 t a = 25c v ref = 2.7v figure 16. supply current vs. supply voltage 04766-015 ch2 50mv/div ch1 2v/div time base 400ns/div 24th clock falling ch1 = sclk ch2 = v out figure 17. digital-to-analog glitch impulse (see figure 21 ) 0 50 100 150 200 250 300 1000 10000 100000 1000000 frequency (hz) noise spectral density (nv/ hz) v dd = 5v t a = 25c v ref = 4.096v full scale midscale zero scale 100 04766-011 figure 18. output noise spectral density 04766-026 ch1 2v/div ch2 2v/div ch3 2v time base = 5.00 s ch2 = v out ch1 = trigger ch3 = sclk figure 19. exiting power-down time to midscale 04766-018 v dd = 3v dac = full scale v ref = 2.7v t a = 25c y-axis = 2v/div x-axis = 4sec/div figure 20. 0.1 hz to 10 hz noise plot 04766-017 50 100 150 200 250 300 350 400 450 500 0 samples amplitude (200v/div) v dd = 5v v ref = 4.096v t a = 25c 10ns/sample figure 21. glitch energy
ad5063 rev. c | page 11 of 20 ?40 ?20 0 20 40 60 80 100 120 140 temperature (c) 04766-010 ?0.010 ?0.008 ?0.006 ?0.004 ?0.002 0 0.002 0.004 0.006 0.008 0.010 gain error (%fsr) gain error @ v dd = 5.5v gain error @ v dd = 2.7v v dd = 5.5v v ref = 4.096v v dd = 2.7v v ref = 2.0v 04766-022 ch1 2v/div ch2 1v/div time base = 100s v dd = 5v v ref = 4.096v ramp rate = 200s t a = 25 c ch1 = v dd ch2 = v out figure 22 . gain error vs. temperature figure 25. hardware power-down glitch 0 2 4 6 8 10 12 14 16 18 20 0.550 0.565 0.580 0.595 0.610 0.625 0.640 0.655 0.680 more bin frequency 04766-049 04766-020 ch1 2v/div ch2 2v/div ch3 20mv/div ch4 2v/div time base 1s/div ch3 = v out ch4 = trigger ch2 = sync ch1 = sclk v dd = 5v v ref = 4.096v t a = 25c figure 26. exiting software power-down glitch figure 23. i dd histogram @ v dd = 5 v 0 5 10 15 20 25 30 35 bin frequen c y 0.465 0. 475 0.485 0.495 0.505 0.515 0.525 0.535 0.545 04766-050 figure 24. i dd histogram @ v dd = 3 v
ad5063 rev. c | page 12 of 2 0 terminology relative accuracy for the dac, relative accuracy, or integral nonlinearity (inl), is a measure of the maximum deviation, in lsb, from a straight line passing through the endpoints of the dac transfer function. a typical inl error vs. code plot is shown in figure 4 . differential nonlinearity (dnl) differential nonlinearity is the difference between the measured change and the ideal 1 lsb change between any two adjacent codes. a specified differential nonlinearity of 1 lsb maximum ensures monotonicity. this dac is guaranteed monotonic by design. a typical dnl error vs. code plot is shown in figure 7 . zero-code error zero-code error is a measure of the output error when zero code (0x0000) is loaded to the dac register. ideally, the output should be 0 v. the zero-code error is always positive in the ad5063 because the output of the dac cannot go below 0 v. this is due to a combination of the offset errors in the dac and output amplifier. zero-code error is expressed in mv. full-scale error full-scale error is a measure of the output error when full-scale code (0xffff) is loaded to the dac register. ideally, the output should be v dd ? 1 lsb. full-scale error is expressed as a percentage of the full-scale range. gain error gain error is a measure of the span error of the dac. it is the deviation in slope of the dac transfer characteristic from ideal, expressed as a percentage of the full-scale range. tot a l un a dju s te d e r ror ( t u e ) total unadjusted error is a measure of the output error, taking all the various errors into account. a typical tue vs. code plot is shown in figure 5 . zero-code error drift zero-code error drift is a measure of the change in zero-code error with a change in temperature. it is expressed in v/c. gain error drift gain error drift is a measure of the change in gain error with a change in temperature. it is expressed in (ppm of full-scale range)/c. digital-to-analog glitch impulse digital-to-analog glitch impulse is the impulse injected into the analog output when the input code in the dac register changes state. it is normally specified as the area of the glitch in nv-s and is measured when the digital input code is changed by 1 lsb at the major carry transition. see figure 17 and figure 21 . figure 17 shows the glitch generated following completion of the calibration routine; figure 21 zooms in on this glitch. digital feedthrough digital feedthrough is a measure of the impulse injected into the analog output of the dac from the digital inputs of the dac, but is measured when the dac output is not updated. it is specified in nv-s and measured with a full-scale code change on the data bus, that is, from all 0s to all 1s, and vice versa.
ad5063 rev. c | page 13 of 20 theory of operation the ad5063 is a single 16-bit, serial input, voltage-output dac. it operates from supply voltages of 2.7 v to 5.5 v. data is written to the ad5063 in a 24-bit word format via a 3-wire serial interface. the ad5063 incorporates a power-on reset circuit that ensures the dac output powers up to midscale. the device also has a software power-down mode pin that reduces the typical current consumption to less than 1 a. dac architecture the dac architecture of the ad5063 consists of two matched dac sections. a simplified circuit diagram is shown in figure 27 . the four msbs of the 16-bit data-word are decoded to drive 15 switches, e1 to e15. each of these switches connects one of 15 matched resistors to either the dacgnd or v ref buffer output. the remaining 12 bits of the data-word drive switches s0 to s11 of a 12-bit voltage mode r-2r ladder network. 2r 04766-027 s0 v ref 2r s1 2r s11 2r e1 2r e2 2r e15 2r v out 12-bit r-2r ladder four msbs decoded into 15 equal segments figure 27. dac ladder structure reference buffer the ad5063 operates with an external reference. the reference input (v ref ) has an input range of 2 v to av dd ? 50 mv. this input voltage is used to provide a buffered reference for the dac core. serial interface the ad5063 has a 3-wire serial interface ( sync , sclk, and din) that is compatible with spi, qspi, and microwire interface standards, as well as most dsps. (see for a timing diagram of a typical write sequence.) figure 2 the write sequence begins by bringing the sync line low. data from the din line is clocked into the 24-bit shift register on the falling edge of sclk. the serial clock frequency can be as high as 30 mhz, making these parts compatible with high speed dsps. on the 24 th falling clock edge, the last data bit is clocked in and the programmed function is executed (that is, a change in the dac register contents and/or a change in the mode of operation). at this stage, the sync line can be kept low or be brought high. in either case, it must be brought high for a minimum of 12 ns before the next write sequence, so that a falling edge of sync can initiate the next write sequence. because the sync buffer draws more current when v ih = 1.8 v than it does when v ih = 0.8 v, sync should be idled low between write sequences for even lower power operation of the part. as previously indi- cated, however, it must be brought high again just before the next write sequence. input shift register the input shift register is 24 bits wide (see figure 28 ). pd1 and pd0 are bits that control the operating mode of the part (normal mode or any one of the three power-down modes). there is a more complete description of the various modes in the power-down modes section. the next 16 bits are the data bits. these are transferred to the dac register on the 24 th falling edge of sclk. sync interrupt in a normal write sequence, the sync line is kept low for at least 24 falling edges of sclk, and the dac is updated on the 24 th falling edge. however, if sync is brought high before the 24 th falling edge, it acts as an interrupt to the write sequence. the shift register is reset and the write sequence is seen as invalid. neither an update of the dac register contents nor a change in the operating mode occurs (see ). figure 31 data bits db15 (msb) db0 (lsb) d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 normal operation 1k ? to gnd 100k ? to gnd three-state power-down modes 0 0 1 1 0 1 0 1 04766-028 000000pd1pd0 figure 28. input register contents
ad5063 rev. c | page 14 of 20 power-on to midscale the ad5063 contains a power-on reset circuit that controls the output voltage during power-up. the dac register is filled with the midscale code, and the output voltage is midscale until a valid write sequence is made to the dac. this is useful in applications where it is important to know the state of the dac output while it is in the process of powering up. software reset the device can be put into software reset by setting all bits in the dac register to 1; this includes writing 1s to bits d23 to d16, which is not the normal mode of operation. note that the sync interrupt command cannot be performed if a software reset command is started. power-down modes the ad5063 contains four separate modes of operation. these modes are software-programmable by setting two bits (db17 and db16) in the control register. tabl e 6 shows how the state of the bits corresponds to the operating mode of the device. table 6. modes of operation for the ad5063 db17 db16 operating mode 0 0 normal operation power-down mode: 0 1 three-state 1 0 100 k to gnd 1 1 1 k to gnd when both bits are set to 0, the part has normal power con- sumption. however, for the three power-down modes, the supply current falls to 200 na at 5 v (50 na at 3 v). not only does the supply current fall, but the output stage is also internally switched from the output of the amplifier to a resistor network of known values. this has the advantage that the output impedance of the part is known while the part is in power-down mode. there are three options: the output can be connected internally to gnd through either a 1 k resistor or a 100 k resistor, or it can be left open-circuited (three-stated). the output stage is illustrated in figure 29 . power-down circuitry resistor network v out ad5063 dac 04766-029 figure 29. output stage during power-down the bias generator, dac core, and other associated linear circuitry are all shut down when the power-down mode is activated. however, the contents of the dac register are unaffected when in power-down. the time to exit power-down is typically 2.5 s for v dd = 5 v, and 5 s for v dd = 3 v (see figure 19 ). microprocessor interfacing ad5063 to adsp-2101/adsp-2103 interface figure 30 shows a serial interface between the ad5063 and the adsp-2101/adsp-2103. the ad sp-2101/adsp-2103 should be set up to operate in the sport transmit alternate framing mode. the adsp-2101/adsp-2103 sport are programmed through the sport control register and should be configured as follows: internal clock operation, active low framing, and 16-bit word length. transmission is initiated by writing a word to the tx register after the sport has been enabled. ad5063 1 additional pins omitted for clarity tfs dt sclk sync din sclk 04766-030 adsp-2101/ adsp-2103 1 figure 30. ad5063 to adsp-2101/adsp-2103 interface 04766-031 db23 db23 db0 db0 invalid write sequence: sync high before 24 th falling edge valid write sequence: output updates on the 24 th falling edge sync sclk din figure 31. sync interrupt facility
ad5063 rev. c | page 15 of 20 ad5063 to 68hc11/68l11 interface figure 32 shows a serial interface between the ad5063 and the 68hc11/68l11 microcontroller. sck of the 68hc11/68l11 drives the sclk pin of the ad5063, and the mosi output drives the serial data line of the dac. the sync signal is derived from a port line (pc7). the setup conditions for correct operation of this interface require that the 68hc11/68l11 be configured so that its cpol bit is 0 and its cpha bit is 1. when data is being transmitted to the dac, the sync line is taken low (pc7). when the 68hc11/68l11 are configured with their cpol bit set to 0 and their cpha bit set to 1, data appearing on the mosi output is valid on the falling edge of sck. serial data from the 68hc11/68l11 is transmitted in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle. data is transmitted msb first. to load data to the ad5063, pc7 is left low after the first eight bits are transferred, and then a second serial write operation is performed to the dac, with pc7 taken high at the end of this procedure. ad5063 1 1 additional pins omitted for clarity pc7 sck mosi sync sclk din 04766-032 68hc11/ 68l11 1 figure 32. ad5063 to 68hc11/68l11 interface ad5063 to blackfin? adsp-bf53x interface figure 33 shows a serial interface between the ad5063 and the blackfin? adsp-bf53x microprocessor. the adsp-bf53x processor family incorporates two dual-channel synchronous serial ports, sport1 and sport0, for serial and multiprocessor communications. using sport0 to connect to the ad5063, the setup for the interface is as follows: dt0pri drives the din pin of the ad5063, tsclk0 drives the sclk of the part, and tfs0 drives sync . adsp-bf53x 1 ad5063 1 1 additional pins omitted for clarity dt0pri tsclk0 tfs0 din sclk sync 04766-033 figure 33. ad5063 to blackfin adsp-bf53x interface ad5063 to 80c51/80l51 interface figure 34 shows a serial interface between the ad5063 and the 80c51/80l51 microcontroller. the setup for the interface is as follows: txd of the 80c51/80l51 drives sclk of the ad5063, and rxd drives the serial data line of the part. the sync signal is again derived from a bit-programmable pin on the port. in this case, port line p3.3 is used. when data is to be transmitted to the ad5063, p3.3 is taken low. the 80c51/80l51 transmits data only in 8-bit bytes; therefore, only eight falling clock edges occur in the transmit cycle. to load data to the dac, p3.3 is left low after the first eight bits are transmitted, and a second write cycle is initiated to transmit the second byte of data. p3.3 is taken high following the completion of this cycle. the 80c51/80l51 output the serial data in a format that has the lsb first. the ad5063 requires its data with the msb as the first bit received. the 80c51/80l51 transmit routine should take this into account. 80c51/80l51 1 ad5063 1 1 additional pins omitted for clarity p3.3 txd rxd sync sclk din 04766-034 figure 34. ad5063 to 80c51/80l51 interface ad5063 to microwire interface figure 35 shows an interface between the ad5063 and any microwire-compatible device. serial data is shifted out on the falling edge of the serial clock and clocked into the ad5063 on the rising edge of the sk. microwire 1 ad5063 1 1 additional pins omitted for clarity cs sk so sync sclk din 04766-035 figure 35. ad5063 to microwire interface
ad5063 rev. c | page 16 of 20 applications table 7. recommended precision references for the ad5063 part no. initial accuracy (mv max) temperature drift (ppm/c max) choosing a reference for the ad5063 to achieve optimum performance of the ad5063, thought should be given to the choice of a precision voltage reference. the ad5063 has one reference input, v ref . the voltage on the reference input is used to supply the positive input to the dac; therefore, any error in the reference is reflected in the dac. 0.1 hz to 10 hz noise (v p-p typ) adr435 2 3 (r-8) 8 adr425 2 3 (r-8) 3.4 adr02 3 3 (r-8) 10 adr02 3 3 (sc-70) 10 there are four possible sources of error when choosing a voltage reference for high accuracy applications: initial accuracy, ppm drift, long-term drift, and output voltage noise. initial accuracy on the output voltage of the dac leads to a full-scale error in the dac. to minimize these errors, a reference with high initial accuracy is preferred. also, choosing a reference with an output trim adjustment, such as the adr423, allows a system designer to trim out system errors by setting a reference voltage to a voltage other than the nominal. the trim adjustment can also be used at any point within the operating temperature range to trim out error. adr395 5 9 (tsot-23) 8 bipolar operation using the ad5063 the ad5063 has been designed for single-supply operation, but a bipolar output range is also possible by using the circuit shown in figure 37 . this circuit yields an output voltage range of 4.096 v. rail-to-rail operation at the amplifier output is achievable using ad8675/ad8031/ad8032 or an op196. the output voltage for any input code can be calculated as because the supply current required by the ad5063 is extremely low, the parts are ideal for low supply applications. the adr395 voltage reference is recommended; it requires less than 100 a of quiescent current and can, therefore, drive multiple dacs in one system, if required. it also provides very good noise performance at 8 v p-p in the 0.1 hz to 10 hz range. ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + ? ? ? ? ? ? = r1 r2 v r1 r2r1d vv dd dd o 536,65 where d represents the input code in decimal (0 to 65,536). with v ref = 5 v, r1 = r2 = 30 k ad5063 3-wire serial interface sync sclk din 7 v 5v v out = 0v to 5v adr395 04766-036 v5 65536 10 ? ? ? ? ? ? ? = d v o this is an output voltage range of 5 v, with 0x0000 corresponding to a ?5 v output and 0xffff corresponding to a +5 v output. 04766-037 ad5063 dacgnd vv ref dd out sclk din sync +5v +4.096 v external op a mp bipolar output 10 f serial interface 0.1 f 0.1 f inv r inv +5v ?5v r fb r fb agnd + figure 36. adr395 as a reference to ad5063 long-term drift is a measure of how much the reference drifts over time. a reference with a tight long-term drift specification ensures that the overall solution remains relatively stable during its entire lifetime. the temperature coefficient of a references output voltage affects inl, dnl, and tue. a reference with a tight temperature coefficient specification should be chosen to reduce the temperature dependence of the dac output voltage on ambient conditions. figure 37. bipolar operation in high accuracy applications, which have a relatively low tolerance for noise, reference output voltage noise needs to be considered. it is important to choose a reference with as low an output noise voltage as practical for the system noise resolution required. precision voltage references, such as the adr435, produce low output noise in the 0.1 hz to 10 hz region. exam- ples of some recommended precision references for use as the supply to the ad5063 are shown in table 7 .
ad5063 rev. c | page 17 of 20 using the ad5063 with a galvanically isolated interface chip in process-control applications in industrial environments, it is often necessary to use a galvanically isolated interface to protect and isolate the controlling circuitry from hazardous common- mode voltages that may occur in the area where the dac is functioning. i coupler? provides isolation in excess of 2.5 kv. because the ad5063 uses a 3-wire serial logic interface, the adum130x family provides an ideal digital solution for the dac interface. the adum130x isolators provide three independent isolation channels in a variety of channel configurations and data rates. they operate across the full range of 2.7 v to 5.5 v, providing compatibility with lower voltage systems as well as enabling a voltage translation functionality across the isolation barrier. figure 38 shows a typical galvanically isolated configuration using the ad5063. the power supply to the part also needs to be isolated; this is accomplished by using a transformer. on the dac side of the transformer, a 5 v regulator provides the 5 v supply required for the ad5063. v dd ad5063 admu1300 power 10f 0.1f gnd 5v regulator sclk v0a v out v0b sync v0c v1a v1b v1c scl k sdi da t a din 04766-039 figure 38. ad5063 with a galvanically isolated interface power supply bypassing and grounding when accuracy is important in a circuit, it is helpful to consider carefully the power supply and ground return layout on the board. the printed circuit board containing the ad5063 should have separate analog and digital sections, each on its own area of the board. if the ad5063 is in a system where other devices require an agnd-to-dgnd connection, the connection should be made at one point only. this ground point should be as close as possible to the ad5063. the power supply to the ad5063 should be bypassed with 10 f and 0.1 f capacitors. the capacitors should physically be as close as possible to the device, with the 0.1 f capacitor ideally right up against the device. the 10 f capacitors are the tantalum bead type. it is important that the 0.1 f capacitor has low effective series resistance (esr) and low effective series inductance (esi), as do common ceramic types of capacitors. this 0.1 f capacitor provides a low impedance path to ground for high frequencies caused by transient currents from internal logic switching. the power supply line itself should have as large a trace as possible to provide a low impedance path and to reduce glitch effects on the supply line. clocks and other fast switching digital signals should be shielded from other parts of the board by a digital ground. avoid crossover of digital and analog signals, if possible. when traces cross on opposite sides of the board, ensure that they run at right angles to each other to reduce feedthrough effects on the board. the best board layout technique is the microstrip technique where the component side of the board is dedicated to the ground plane only, and the signal traces are placed on the solder side. however, this is not always possible with a 2-layer board.
ad5063 rev. c | page 18 of 20 compliant to jedec standards mo-187-ba outline dimensions 0.23 0.08 0.80 0.60 0.40 8 0 0.15 0.05 0.33 0.17 0.95 0.85 0.75 seating plane 1.10 max 10 6 5 1 0.50 bsc 3.10 3.00 2.90 pin 1 5.15 4.90 4.65 3.10 3.00 2.90 coplanarity 0.10 figure 39. 10-lead mini small outline package [msop] (rm-10) dimensions shown in millimeters ordering guide model temperature range inl settling time pa ckage description package option branding ad5063brmz 1 ?40c to +85c 1 lsb 4 s typ 10-lead msop rm-10 d49 ad5063brmz-reel7 1 ?40c to +85c 1 lsb 4 s typ 10-lead msop rm-10 d49 ad5063brmz-1 1 ?40c to +85c 1 lsb 1 s max 10-lead msop rm-10 dcg ad5063brmz-1-reel7 1 ?40c to +85c 1 lsb 1 s max 10-lead msop rm-10 dcg EVAL-AD5063EB evaluation board 1 z = rohs compliant part.
ad5063 rev. c | page 19 of 20 notes
ad5063 rev. c | page 20 of 20 notes ?2005C2009 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d04766-0-8/09(c)

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